1. Field of the Invention
The present invention relates to an access method and architecture of a computer memory, and more particularly to a multi-access mechanism having a pragmatic bit to determine either a non-volatile random access memory (NVRAM) or a computer peripheral controller device is the controlled device.
2. Description of the Related Art
In a use of a Non-Volatile Random Access Memory (NVRAM), the NVRAM can be directly coupled to a host via a 3-wire or a 4-wire mechanism. The host is a device equipped with a central processing unit (CPU) level of processing unit. It has the ability of independently executing an application program. As shown in FIG. 1A, a NVRAM is coupled to the host via a 3-wire mechanism, wherein CS is a chip-select line, SK is a system-clock line, and DI/DO is a data-input/data-output line. As shown in FIG. 1B, a 4-wire mechanism is employed to connect the host and a NVRAM, wherein CS is a ship-select line, SK is a system-clock line, DI is a data-input line, and DO is a data-output line. Apparently, the major difference between the 3-wire and the 4-wire mechanisms is that the data-input and data-output lines are integrated in a single line in the 3-wire mechanism. Signals transmitted between the host and a NVRAM are depicted in FIG. 2. As shown in FIG. 2, data stored in the NVRAM are read to the host. During a period when CS is at a high potential level or logic 1 state, the NVRAM is selected and is enabled to respond to an instruction issued by the host. The system clock synchronizes the instruction and data transmission. In FIG. 2, a “READ” command comprising Ai to A0 is transmitted to the NVRAM at the third clock pulse via the data-input line. During the command transmission, the data-output line is in high-impedance mode (Hi-Z). After receiving the command from the host, the NVRAM responds by sending a sequence of data (Dj˜D0) via the data-output line. The NVRAM with the 3-wire or 4-wire mechanism has been widely used for years in the computer industry for its simple instructions and easy implementation of hardware interface.
Accordingly, in a NVRAM with a 3-wire or 4-wire mechanism, a host to a NVRAM is conventionally a one-to-one architecture such that the host can only select or enable one device, i.e., the NVARM. As the use of computers expands, computers are built in more functions and higher capacities. The conventional one-to-one architecture is considered inefficient and wasteful in system resources of the computers.
Therefore, there is a need to use a host to control not only a NVRAM but also some other peripheral devices, such as a RS-232 I/O controller or a micro-controller, so as to enhance the processing capacity and the performance of the system.